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mipspipelinecpu-architecture

MIPS - Forwarding in static multiple-issue

On a static two-issue pipeline for MIPS, can I use the forwarding paths with two instructions running in the same clock cycle?

For example:

1. add $t0, $t0, $t1 2. sw $t0, 0($t2)

Can I execute these two instructions on the same clock cycle? The sw could use the resulting value of the add when it is going to execute the MEM stage.

Is that correct?

Solution

  • If you consider a typical 5 stage pipeline (IF, ID, EX, MEM, WB), the output of the ADD will be available at EX -> MEM interface. For the MEM stage of the SW instruction, it needs the memory address, which is 0 + ($t2) and the data which is supposed to be in $t0. However $t0 has not been updated yet, as the pipeline has not reached WB stage. However the value which is supposed to be written to $t0 is available at EX->MEM stage. Therefore, you can use forwarding in this scenario to execute SW instruction without waiting for ADD to complete.