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chisel

Disable FIRRTL pass that checks for combinational loops


Is there a way to disable the CheckCombLoops FIRRTL pass? (These loops are false.) If possible, I want to do this in the tester driver. I saw the option for the FIRRTL intepreter, but I still get an exception during the FIRRTL run. I also want to be able to use VCS as a backend.

class LazyStackNWait2Test extends FlatSpec with Matchers {
  behavior of "LazyStackNWait2"
  it should "work" in {
    chisel3.iotesters.Driver.execute( Array( "--fr-allow-cycles", "--backend-name", "firrtl"), () => new LazyStackN(10, () => new LazyStackWait2)) { c =>
      new LazyStackNTester( c)
    } should be ( true)
  }
}

Here is part of the log:

[info] [1.057] Done elaborating.
[info] - should work *** FAILED ***
[info]   firrtl.passes.PassExceptions: 
firrtl.passes.CheckCombLoops$CombLoopException:  @[:@5437.2]: [module LazyStackN] Combinational loop detected:

The build is from the latest github HEAD.


Solution

  • EDIT: This is now supported via the --no-check-comb-loops. Relevant PR

    There currently is not a way but I've created an issue to add this feature and it shouldn't be that difficult to do. https://github.com/ucb-bar/firrtl/issues/600

    Just out of curiosity, what kind of false combinational loops are you seeing? We find that they are pretty rare* and usually easy to work around, so if you have any examples you can share I would greatly appreciate it.

    * For example, they usually happen with aggregate types that have a dependence between subelements if the aggregate gets cast to bits and back (through a chisel3.util.Mux1H for example). Just trying to see what other common use patterns can cause false loops.