Search code examples
veriloghdl

How do you get a parameter of unknown width?

I want a parameter of unknown width for a design.
Something like this generic in VHDL. 

Generic (xyz : std_logic_vector);

How is this done?

Solution

  • Verilog parameters assume the width of the value assigned to them.

    module foo();
parameter xyz = 1'b0;
initial $display("%m %b",xyz); // display foo 0 by itself
endmodule
module top;
foo #(3'b0) f1(); // will display top.f1 000
foo #(4'b0) f1(); // will display top.f2 0000
endmodule