I would like to initialize the memory bitmem by setting all bits to 1 when intialized for the first time. I have seen inits used for ROM, and I wonder if there are similar ways to initialize value in Mem?
val bitmem = Mem(Bits(width = conf.ways), (conf.cache_lines*conf.words_per_line)
Chisel is first and foremost intended for designing ASICs. As such, the focus is on synthesizable hardware so that when you simulate your Chisel code, you are simulating the same thing you are synthesizing. Since Mem is intended to map to SRAMs in an ASIC and SRAMs cannot be initialized, we do not support this construct in Chisel itself. If you wish to create registers instead of an SRAM, try Reg of Vec.
However, the ability to initialize Mems is clearly a useful feature for simulation. We are in the process of revamping the Chisel Testers and this feature is intended to be a first class feature. We are also discussing what Chisel API could help users initialize their memories in Verilog or SystemVerilog testbenches.
In the meantime as a workaround, you could parameterize your design based on whether the memory (or memories) should by initialized (ie. if you're elaborating for simulation or synthesis), and emit a Reg of Vec when you are simulating and a Mem when you are not.