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chisel

How to Initialize a Register of Vectors?

I have defined a register of vectors like this

val my_reg = Reg(Vec(n, Bits(32.W)))

and I access the elements of this register in a for loop using my_reg(i).

Now, I like to initialize this register to zero, so I change the variable definition to this

val my_reg = Reg(Vec(n, Bits(32.W)), init = UInt(0))

However, I get the following compilation error when I want to access the elements of this register

chisel3.core.Data does not take parameters
my_reg(i) := io.a(i)

How can I define a register of vectors and properly initialize them synchronously?

Solution

  • Use RegInit instead. I believe the following statement will do what you want

        val my_reg = RegInit(Vec(Seq.fill(n)(0.U(32.W))))

    The Vector is initialized by a Seq of UInt zeros that are 32 bits wide