I am using iverilog
on a Mac, and I have problem compiling some codes that include always_ff
and always_comb
blocks. ModelSim compiles those codes without any problem. Is it possible to configure iverilog
so as to support always_ff
and always_comb
blocks, or they are just not supported by the compiler?
always_comb
, always_latch
and always_ff
are some of the keywords that were introduced in the SystemVerilog IEEE Std 1800-2012. They are not part of the Verilog IEEE Std 1364-2005, which is what the Icarus Verilog compiler supports.
I am not aware of any free SystemVerilog simulators. However, you can always simulate and synthesize your SystemVerilog design using EDA Playground.