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vhdlhdlxilinx-isedigital-logic

Entity Instantiation Inside of a Process


I am trying to make a two dimensional array of full adders with specific logic with their inputs and outputs. I currently have two for-generate statements of rows and columns, and then an if-elsif-else statement to decide how to connect that full adder. My code looks like this:

   rows : for row in 0 to n-1 generate
    columns : for col in 0 to n-1 generate
            if row = 0 then 
                null;
            elsif row = 1 then
                first: entity work.fa
                port map (  A => Ain(row)(col),
                                B => Bin(row)(col),
                                sum => sum(row+1)(col),
                                cin => cin,
                                cout => cout(row)(col+1)
                             );
            else
                process begin
                if (row = n/2) then
                    last: entity work.fa
                    port map ( A => Ain(row)(col),
                                B => Bin(row)(col-offset),
                                sum => sum(row)(col-offset),
                                cin => cin,
                                cout => cout(row)(col)
                             );
                else
                    middle: entity work.fa
                    port map (  A => mandq(row)(col-offset), 
                                B => sout(row)(col-offset),
                                sum => sout(row)(col-offset),
                                cin => cout(row)(col),
                                cout => cout(row)(col+1)
                             );
                end if;
                end process;
            end if;
            end process;
    end generate;
 end generate;

each entity is getting the following errors: - Syntax error near "entity". - Syntax error near "port". - Syntax error near ";".

The "entity" error is occuring on the lines titled first, middle and last

The "port" issue is occurring on the lines immediately after the entities.

The ";" issue is occuring on lines that contain the port map ending );


Solution

  • You should not use if .. then, but instead use if .. generate. In VHDL-2008 this has become really easy, as elsif .. generate etc is supported. Or even case ... generate

    You could write it like this:

    rows : for row in 1 to n-1 generate -- shouldn't this only go to (n/2) ?
        columns : for col in 0 to n-1 generate
            element: case row generate
                -- when 0 no longer occurs with modified range
                when 1 =>
                    first: entity work.fa
                    port map (
                        A => Ain(row)(col),
                        B => Bin(row)(col),
                        sum => sum(row+1)(col),
                        cin => cin,
                        cout => cout(row)(col+1)
                        );
                when n/2 =>
                    last: entity work.fa
                    port map (
                        A => Ain(row)(col),
                        B => Bin(row)(col-offset),
                        sum => sum(row)(col-offset),
                        cin => cin,
                        cout => cout(row)(col)
                        );
                when others =>
                    middle: entity work.fa
                    port map (
                        A => mandq(row)(col-offset), 
                        B => sout(row)(col-offset),
                        sum => sout(row)(col-offset),
                        cin => cout(row)(col),
                        cout => cout(row)(col+1)
                        );
            end generate;
        end generate;
    end generate;