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How to create a Vecs of register by Chisel

I will use Chisel3 to construct a register set. The Chisel code is:

 val register_set = Reg(Vec(7,UInt(32.W)))

But the synthesized Verilog code is:

 reg [31:0] register_set_0;
 reg [31:0] register_set_1;
 reg [31:0] register_set_2;
 reg [31:0] register_set_3;
 reg [31:0] register_set_4;
 reg [31:0] register_set_5;
 reg [31:0] register_set_6;

How should I change my Chisel code in order to synthesize the Verilog code like this:

reg [31:0]  register_set [0:6];
Solution

  • Chisel currently cannot emit Verilog arrays. This is obviously a highly desirable feature and is on our TODO list but it is not yet implemented.