Search code examples
verilogsystem-verilogunionsverification

Unpacked union in SystemVerilog

typedef union {
      logic [1:0] c3; 
      bit [3:0] a3; 
      byte b3; 
  } pack3;

pack3 p3;

According to the LRM, the default initialization is according to the first member of the union, i.e., logic in the above example. Therefore, c3 assign to X and rest to assign to 0. But, when I compile in ModelSim and check in object window, then there is a different result for a3 and b3.

Also when I assign p3.a3 = 4'b0010;, the value of a3 and b3 changes but not c3. Please explain. I know there is only memory available for each variable, so update in any value reflects all.

Solution

  • There are no guarantees if you write to one member of an unpacked union and try to read another member (except for one special provision mentioned at the end of section 7.3 Unions in the 1800-2012 LRM). You need to use a packed union if you want a guarantee in the layout of overlapping members.