Search code examples
chisel

Not bound to synthesizable node exception and type mismatch error in chisel

I have the following chisel function.

def apply(din: Bits, typ: Bits): Vec[UInt] =
{
    val word    =   (typ.equals(MT_W)) || (typ.equals(MT_WU))
    val half    =   (typ.equals(MT_H)) || (typ.equals(MT_HU))
    val byte    =   (typ.equals(MT_B)) || (typ.equals(MT_BU))

    val dout    =   Wire(Vec(4, UInt(8.W)))
    dout        :=      Mux(Bool(byte), Vec(4, din( 7,0)),    //line 119
                Mux(Bool(half), Vec(din(15,8), din( 7,0), din(15,8), din( 7,0)),
                        Vec(din(31,24), din(23,16), din(15,8), din( 7,0))))

    return dout
}

Reassignment to dout gives a Not bound to synthesizable node exception regardless it being defined as a wire.

[info] - should correctly write and read data *** FAILED ***
[info]   chisel3.core.Binding$BindingException: 'con' (Vec(chisel3.core.UInt@133, chisel3.core.UInt@134, chisel3.core.UInt@135, chisel3.core.UInt@136))(*): Not bound to synthesizable node, currently only Type description
[info]   at chisel3.core.Binding$.checkSynthesizable(Binding.scala:184)
[info]   at chisel3.core.Mux$.doMux(Bits.scala:770)
[info]   at chisel3.core.Mux$.doAggregateMux(Bits.scala:785)
[info]   at chisel3.core.Mux$.do_apply(Bits.scala:764)
[info]   at Common.StoreDataGen$.apply(memory.scala:119)
[info]   at Common.OnChipMemory$$anonfun$1$$anonfun$apply$1.apply$mcV$sp(memory.scala:97)

So I thought it's probably due to something with the return statement. Just to check I ran the code without the return. Then it gives a type mismatch at line 119. (Removing the Mux didn't help either)

[error] /home/.../memory.scala:119: type mismatch;
[error]  found   : Unit
[error]  required: chisel3.Vec[chisel3.UInt]
[error]     (which expands to)  chisel3.core.Vec[chisel3.core.UInt]
[error]         dout        :=      Mux(Bool(byte), Vec(4, din( 7,0)),
[error]                     ^

I must be doing something terribly wrong here. But I can't figure out what it is.

Solution

  • This issue is with the connection to dout (Note that := is the Chisel operator for connection not reassignment which is a Scala operator). Consider the abridged version below:

    dout        :=      Mux(Bool(byte), Vec(4, din( 7,0)), ...)

    Specifically, Vec(4, din( 7,0)) is actually constructing a Vec Type of size 4 with elements of type Bits(8.W). The error is referring to this Vec type, not dout itself.

    What exactly are you trying to do here, are you trying to repeat din(7,0) 4 times? If so, try this: Vec(Seq.fill(4)(din(7,0))). That will create a Wire for you to Mux.