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macrossystem-veriloguvm

Error - near ":": syntax error, unexpected ':', expecting IDENTIFIER or clock


I created my own my_macros file:

`ifndef MY_MACROS_SV
`define MY_MACROS_SV

// MACRO: 'my_fatal_err
// calls uvm_fatal in case the assertion is not correct
`define my_fatal(condition, msg )\
   assert (condition) else\
`uvm_fatal("FATAL ERROR", msg)\
\
`define add_rand(mem_type, mem)\
   case (mem_type)\
     "int": add_rand_int(mem);\
     "bit": add_rand_bit(mem);\    
     default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
     endcase  



`endif  //MY_MACROS_SV

mem_type expects a string, and mem is a member of class.

I got the following compilation error:

at ..\sv\my_macros.sv(19): near ":": syntax error, unexpected ':', expecting IDENTIFIER or clock.

Line 19 is the default:


Solution

  • Separate your 2 macros:

    `ifndef MY_MACROS_SV
    `define MY_MACROS_SV
    
    // MACRO: 'my_fatal_err
    // calls uvm_fatal in case the assertion is not correct
    `define my_fatal(condition, msg )\
       assert (condition) else\
    `uvm_fatal("FATAL ERROR", msg)
    
    `define add_rand(mem_type, mem)\
       case (mem_type)\
         "int": add_rand_int(mem);\
         "bit": add_rand_bit(mem);\    
         default: `uvm_fatal("FATAL ERROR", "type is not supported")\ 
         endcase  
    
    
    
    `endif  //MY_MACROS_SV