uvm_reg peek function takes long time to return

Question

I thought the peek function of uvm_reg returned the value in 0 simulation time. Since I needed this functionality, I implemented all my HDL backdoor access paths. This is the code I am using in my scoreboard

while (state == DISABLE) begin
  uvm_reg_data_t val = 'hDEADBEEF;
  uvm_status_e status;
  `uvm_info(get_name(), "Start peek", UVM_LOW)

  my_reg_block.my_reg.peek(status, val);

  `uvm_info(get_name(), "End peek", UVM_LOW)

  assert (val == 'h0)

  @posedge(my_vif.clk); //Advance clock

end

My intention was: On every clock cycle, in zero simulation time, assert that my_reg is 0 when the state==DISABLE.

In simulation run, I notice this is fine until around the time that my_reg is changing. At the point, Start peek -> End peek takes about 10 clock cycles. In this time, my state is no longer DISABLE and ofcourse val != 'h0. Why does peek take so long to return?

I am using Questasim 10.4a

Answer 1

It may take some time, because peek is a SystemVerilog task, not a function.

Function will be executed in 0 Simulation Time, but Tasks can have the timing delays as well.

Here is it's definition.

virtual task peek(  output  uvm_status_e    status,     
output  uvm_reg_data_t  value,      
input   string  kind     =  "",
input   uvm_sequence_base   parent   =  null,
input   uvm_object  extension    =  null,
input   string  fname    =  "",
input   int     lineno   =  0   )