I wish to know how many LPM_DIV (Altera dividers) can I generate in one single project if my FPGA board is the 5CSEMA5F31C6N DE1-SOC.
I am intending to do a project on which I have to process data through many dividers working at the same time (same clock), the total amount varies, ranging from be 4 and 4096. I wonder if this is somehow feasible in the FPGA.
PD: A friend have told me that it is in fact feasible to generate this large amount of dividers, but only in simulation, but not to synthesize in the FPGA, that Quartus II would give me a report on which says how many logic gates I lack to complete the requirement.
Remember that HDL instantiates physical circuitry, and those circuits don't just magically disappear because you no longer need them. You would need to design your system to always have all 4096 dividers, and only take the outputs from the ones you use.
The number of dividers depends on how you have them configured: input sizes, pipelining, optimization method. One 64/64 divider with registered output uses ~2300 (7%) of the ALMs on the DE1-SoC, meaning you could fit ~14 dividers on the chip. Using different input parameters, you'd get different results.
If you synthesize one of your dividers, Quartus will give you a percent of resources used for each type. From that, it should be easy to determine the number of dividers you can fit.