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veriloghdlsynthesis

Is event trigger synthesizable in verilog?

I am trying to use event triggering in my code (->). Will this get synthesized? 

always @(posedge clk) begin
count <= count + 1;
-> x;
end

always @(x) flag = 1;

This is just a sample code. What i want to do is when ever there is an event in the count I want to make the flag high, else it should remain low. In my case the count value increases after every 7 clock cycles. Can i use event triggering for this? If not what can I do to meet my requirement?

Solution

  • Anything you can execute in simulation could be synthesized if tools choose to support it. But most RTL synthesis tools do not support this.

    In your simple case, you could replace your event trigger with a task call (or void function call in SystemVerilog).

     always @(posedge clk) begin
  count <= count + 1;
  x;
end
task x;
flag <= 1;
endtask