compile and simulate an UVM TB in Modelsim 10.4b

Question

I am new to using UVM in modelsim 10.4b. I am trying to check if my class is getting compiled, but I am getting the following compilation error. Also, if anyone can point me to the UVM exection flow, that would be really helpful. I have searched on the online resources.

class fifo_trans_item extends uvm_sequence_item;

    rand bit [15:0] data_in;
    rand bit push;
    rand bit pop;
    rand bit w_en;
    rand bit r_en;

endclass

This is the error I am getting.If this is a tool related issue, please redirect me to the forum for asking this question.

Loading project MIPS
# reading modelsim.ini
# Loading project UVM_tb
# UVM Details: design does not contain any  UVM components, UVM debugging is disabled, or an  unknown questa_uvm_pkg has been loaded.
# Compile of sequence.sv failed with 2 errors.

** Error: (vlog-13069) /afs/asu.edu/users/s/m/u/smukerji/sequence.sv(1): near "uvm_sequence_item": syntax error, unexpected IDENTIFIER.
** Error: /afs/asu.edu/users/s/m/u/smukerji/sequence.sv(1): Error in class extension specification.

Answer 1

You need

import uvm_pkg::*;
`include "uvm_macros.svh"

in every file that references the UVM base class library and macros