I am trying to use a ternary operator inside an always block, is it synthesizable. And is MOD (%) operator synthesizable in verilog? because when i am simulating the code the results appear to be correct and when implemented in hardware its acting weird. I have studied some where that division operator is also not synthesizable until unless the divider is a power of 2. Is it true? I am using vivado tool to synthesize my code.
As per my knowledge, ternary operator is synthesizable, as it can be mapped to a simple 2*1 multiplexer theoritically.
I am not sure, but mod(%) operator won't be synthesizable. Multiplication, Division, Modulo, these are programming terminology, but for real hardware, you would actually require a hardware, which does multiplication or division or modulo operation. So tool can't make that hardware, just by % in your code.
One reference for synthesizable verilog constructs - http://asic-soc.blogspot.in/2013/06/synthesizable-and-non-synthesizable.html