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system-verilogassertuvm

Is there a specific way to stop the test/simulation in case condition failure?

I want the test to stop in the case of a failure condition. I used UVM_ERROR, but this only produces a text message. Is there a specific way to stop the test/simulation in case condition failure in addition to the text message (something like assert in systemVerilog)?

Solution

  • Add the +UVM_MAX_QUIT_COUNT=1 runtime option on your simulator command line. This will end the simulation after the 1st UVM_ERROR.