This might be a very simple but a bit longer question and I would appreciate all the help!
Here's what we have: an FPGA card (Spartan-3e to be precise) - 8 switches, 8 LEDs, and a very simple Verilog code:
module Lab1_1(
input [7:0] sw,
output [7:0] ld
);
assign ld = sw;
endmodule
This connects the switches to the LEDs so when sw[0] is 1, then ld[0] is also 1 (or at least intended to do be), etc.
The exercise to this (shortened and translated into English):
"We assume the following types of errors in our PCB:
- the signal is not transmitted (the conductor is torn)
- the signal is stuck at 0 or 1
- any two or more neighboring signals get into short-circuit (not possible with non-neighboring!)
With these kinds of errors, how many and what kinds of test vectors do we need to make sure that the check is comprehensive? (At most we have 256 test vectors, which seems a bit too much.)"
I would be really thankful for anything that helps me understand the problem or the way I should start with the solution! :)
the signal is not transmitted (the conductor is torn)
All signals must be exercised in both 0 and 1 states.
the signal is stuck at 0 or 1
1 -> 0 -> 1 or 0 -> 1 -> 0 transitions must be exercised for all bits
any two or more neighboring signals get into short-circuit (not possible with non-neighboring!)
Do you know which nets might be neighbouring after routing on the FPGA? In that case: All neighbouring signals must be exercised in complementary 0 -> 1 -> 0 and 1 -> 0 -> 1 states. I.e. 'hAA -> 'h55 -> 'hAA
Short circuit checks also require you to monitor the current consumption during the test.
But note that I don't think there is any guarantee that bits that are neighbouring in RTL are neighbours in the routed FPGA.