I recently started working with FPGAs and have been trying to get a basic VHDL program up and running. My code is intended to take the inputs from 10 switches and map them to 10 LED outputs on my dev board, but when I attempt to run analysis/synthesis I get the error in the title. Analyzing the file individually by running "Analyze Current File" yields no errors. A similar post was made here, but the solution there does not help me. I have only one file in my project and I am certain that it has been specified as the top-level entity.
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity sw_to_led is port(
SW: in bit_vector(9 downto 0);
LED: out bit_vector(9 downto 0));
end sw_to_led;
architecture behavior of sw_to_led is
begin
LED <= SW after 5ns;
end behavior;
1) Is the name of the vhdl file the same as the entity name sw_to_led.vhd ?
2) Are there already partitions in your design? If yes, you can try making a new Quartus-Project with the help of the "New Project Wizard" and add only the file sw_to_led.vhd.
By the way, after 5ns is not synthesizable. It should only be used in the simulation. But for Quartus it's not an error.