Chisel: Verilog generated code for Sint and UInt

Question

When using SInt and UInt to implement an adder I get the same Verilog code, see the codes below,

import Chisel._

class Unsigned_Adder extends Module{ 
  val io = new Bundle{
    val a =      UInt(INPUT, 16)
    val b =      UInt(INPUT, 16)
    val out =    UInt(OUTPUT)
  }
  io.out := io.a + io.b
}

and

 import Chisel._

class Signed_Adder extends Module{ 
  val io = new Bundle{
    val a =      SInt(INPUT, 16)
    val b =      SInt(INPUT, 16)
    val out =    SInt(OUTPUT)
  }
  io.out := io.a + io.b
}

This will generate the same Verilog code,

module Signed_Adder(
    input [15:0] io_a,
    input [15:0] io_b,
    output[15:0] io_out
);

  wire[15:0] T0;


  assign io_out = T0;
  assign T0 = io_a + io_b;
endmodule

Of-course the modules names will differ. when implementing a multiplier in chisel using the multiplication operator (*)

io.out := io.a * io.b  

I will get a different Verilog code for the UInt and SInt, where in the SInt the code will look like,

module Multi(
    input [15:0] io_a,
    input [15:0] io_b,
    output[31:0] io_out
);

  wire[31:0] T0;


  assign io_out = T0;
  assign T0 = $signed(io_a) * $signed(io_b);
endmodule

Adding $signed to the code. Why is that? why is it that in the addition case I get the same Verilog code but in the multiplication case I get a different code generated for UInt and SInt?

Answer 1

With addition if the size of variable are equal, the adder don't care about the sign, the addition will be correct thanks to overflow bit. But with multiplication, we have to know the sign to manage it.

See this documentation about the signed arithmetic in verilog for more information : enter link description here