Syntax error near end in Verilog

Question

I'm writing a Verilog code to give all possible combinations of inputs to a 4:1 multiplexer. Here is the testbench for the same to test the code:

module FouthQuestion_tb;

reg d0, d1, d2, d3, s0, s1;
wire y;
reg o;

FourthQuestion mygate(.D0(d0), .D1(d1), .D2(d2), .D3(d3), .S0(s0), .S1(s1), .Y(y));

initial
begin
    $monitor(d0, d1, d2, d3, s0, s1, y);
    for(d0=0; d0<=1; d0=d0+1)
    begin
        for(d1=0; d1<=1; d1=d1+1)
        begin
            for(d2=0; d2<=1; d2=d2+1)
            begin
                for(d3=0; d3<=1; d3=d3+1)
                begin
                    for(s0=0; s0<=1; s0=s0+1)
                    begin
                        for(s1=0; s1<=1; s1=s1+1)
                        begin
                            #5
                        end
                    end
                end
            end
        end
    end
end

endmodule

However, I'm always getting the error "syntax error near end". What could be the possible syntactical mistake that is being made here?

Answer 1

The problem (aside from the missing semicolon after #5) is that the loop condition is <= 1, which will always be true for a boolean type (having the only possible values 0 and 1). Thus it never exits the inner loop and instead runs forever toggling only s1.

You should instead use loop variables that can take on values larger than the one you are comparing, such as int. To simplify, you can use a single loop variable that contains at least one more bit than all your boolean variables put together, then assign the multi-bit result to each variable through concatenation. See the following example.

integer i;

initial begin
  $monitor(d0, d1, d2, d3, s0, s1, y);
  for (i=0; i<2**6; i=i+1) begin
    {d0,d1,d2,d3,s0,s1} = i;
    #5;
  end
end