Verilog: Store bits into a specific range of bits of an initialized module

Question

So I have been following a guide provided by EmbeddedMicro on producing a simple 16 bit CPU using their HDL Lucid. My goal is to convert this over to Verilog in Quartus II. The problem I am having is trying to store the bits allocated for the destination of my data into a specific range of bits inside the designated register. The second problem I am having is using a global Constant as one of case values. I was able to get around this by just replacing with the constant value. I have already added the include file into the project settings. I am still new to Verilog so their might be an abundant of bad code.

The error recieved is on line 57

    shift_r.D[DEST] = DIN; //supposed to be storing the data coming in into register

Error Readout: Verilog Syntax Error, near text: "=". Check for and fix any syntax errors that appear immediately before or at the specified keyword

`include "CPU_8/my_incl.vh"


module CPU(CLK,RST,WRITE,READ,ADDRESS,DOUT,DIN);
input RST,CLK;
input [0:7] DIN; //DATA in
output reg [0:7] ADDRESS;
output reg [0:7] DOUT; //DATA OUT
output reg WRITE,READ;

reg [0:15] INST;



//I am not sure if i set up the array for my registers correctly either
shiftreg shift_r[0:15] (RST, CLK, D, Q); //initialize shift_r and create array of 16 registers.
//Implicit net is created for the D and Q above when generating block file 

instRom_16 instRoms(ADDRESS, INST); //intialize InstRom_16 module



reg [0:3]OP;        // opcode
reg [0:3]ARG1;      // first arg
reg [0:3]ARG2;      // second arg
reg [0:3]DEST;      // destination arg
reg [0:7]CONSTANT;  //Constant



always@(posedge CLK)
begin
    WRITE = 0;      // don't write
    READ  = 0;       // don't read
    ADDRESS = 8'b0; // don't care
    DOUT = 8'b0;    // don't care

    instRoms.ADDRESS = shift_r.D[0]; //Set shift_reg to be program counter
    shift_r.D = shift_r.Q[0] + 1;   //increment program counter.




    OP = instRoms.INST[15:12]; // opcode first 4 bits
    DEST = instRoms.INST[11:8]; // destination one 4 bits
    ARG1 = instRoms.INST[7:4]; // argument2 is next 4 bits
    ARG2 = instRoms.INST[3:0];  // ARGUMENT2 is last 4 bits
    CONSTANT = instRoms.INST[7:0];

    //PERFORM OPERATIONS
        case (OP)
            4'd1: //tried to use `LOAD but that wouldn't point to the value in my include file
                READ = 1;                                 // request a read

                //line that is failing
                shift_r.D[DEST] = DIN; //supposed to be storing the data coming in into register

         //4'd2:


    endcase

    end


endmodule

This is my include file

`ifndef _my_incl_vh_
`define _my_incl_vh_

`define NOP   = 4'd0;  // 0 filled

`define LOAD  = 4'd1; // load

`endif

Answer 1

You made a little mistake:

shiftreg shift_r[0:15] (RST, CLK, D, Q);

Instantiates an array of shift_r, each instance of which has a RST, CLK, D and Q.

So shift_r.D[DEST] should become shift_r[DEST].D and shift_r.Q[0] should become shift_r[0].Q.

For shift_r.D, is guess you want a 0:15 vector. You will need to assign all 16 bits to an intermediate wire of 15 bits using e.g. a for loop.