My goal is to form this code with Quartus, but the problem is I don't know how to fix the problem. I've tried to know what Error 10028 means, but I cant figure out how to work with it. Can someone teach me how to fix it or if there's a way to bypass it?
module mem (r_wb,addr,d,q);
input r_wb;//0write 1read
input [7:0] addr;
input [7:0 ] d;
output [7:0] q;
reg [7:0] q;
reg [7:0] mem_bank [0:255];
always @(r_wb)
if (r_wb) q=mem_bank[addr];
else mem_bank[addr]=d;
always @(addr)
if (r_wb) q=mem_bank[addr];
else mem_bank[addr]=d;
always @(d)
if (r_wb) q=mem_bank[addr];
else mem_bank[addr]=d;
endmodule
The code you put in your comment is mostly correct in the fact that you do need a clocking signal. However you should be using non-blocking assignment (<=).
I would recommend changing your model header to ANSI style which has been around since 2001. The non-ANSI style required q the be identified three times; port list, direction, type. ANSI style compacts it. Non-ANSI is good to understand because a lot of synthesizers and code generators still use it by default. But any modern simulator or synthesizer will accept ANSI style as input.
module mem (
input clk,
input r_wb, //0write 1read
input [7:0] addr,
input [7:0 ] d,
output reg [7:0] q) ;
reg [7:0] mem_bank [0:255];
always @(posedge clk)
if (r_wb) q<=mem_bank[addr];
else mem_bank[addr]<=d;
endmodule