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fpgaxilinxvivado

How to see content of look up table

Imagine we have a simple code for fpga, I want to know if there is any way to watch content of specific lookUp table after synthesis, actually that data that will be written in SRAM

module test8(a,b,c

    );
    input a ; 
    input b ;
    output c;

    assign c = a&b;

endmodule

Simple AND gate

Solution

  • The possibility depends on the FPGA vendors tool.

    Some tools has a GUI floor-plan view where the used LUTs can be found, and these LUTs can then have associated code attached for the memory contents of the LUT. In Altera Queatus Chip Planner it may look like:

    enter image description here

    Another option is to generate a netlist of the complete design, usually writable from the FPGA tool, and this netlist will then contain the LUTs together with code for the LUT contents. In Altera Quartus generated Verilog netlist it may look like:

    ...
// Location: LABCELL_X10_Y34_N0
cyclonev_lcell_comb \c~0 (
// Equation(s):
// \c~0_combout  = ( \a~input0  & ( \b~input0  ) )

    .dataa(gnd),
    .datab(gnd),
    .datac(!\b~input0 ),
    .datad(gnd),
    .datae(gnd),
    .dataf(!\a~input0 ),
    .datag(gnd),
    .cin(gnd),
    .sharein(gnd),
    .combout(\c~0_combout ),
    .sumout(),
    .cout(),
    .shareout());
// synopsys translate_off
defparam \c~0 .extended_lut = "off";
defparam \c~0 .lut_mask = 64'h000000000F0F0F0F;
defparam \c~0 .shared_arith = "off";
// synopsys translate_on
...

    Note that the GUI view shows that the AND gate is not implemented using just a single simple LUT, since the tools has the freedom to implement it as it seems fit, as long as any timing and other requirements are observed.

    But in the end, the specific implementation and considerations about LUT coding is usually ignored by the designer... except in special debugging cases.