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memoryverilogquartustest-bench

In Verilog, I'm trying to use $readmemb to read .txt file but it only loads xxxxx (dont cares) on memory


I need to load a memory with some data originally in binary. I read that $readmemb can be use for this, and there is even a method to make synthesizable.

So, I created another module named RAM_IN (which is not the testbench module) and "connected" to the top module.

Before knowing about $readmemb, I was using this code:

initial
begin
in_ram [0] <= 32'b11111111_000000000000000000000000; 
in_ram [1] <= 32'b10010111_000000000000000000000000;
in_ram [2] <= 32'b00110110_000000000000000000000000;
in_ram [3] <= 32'b00111110_000000000000000000000000;
in_ram [4] <= 32'b00111111_000000000000000000000000;
in_ram [5] <= 32'b00111110_000000000000000000000000;
end

But its too tiring for me to write 100 numbers like this, so implemented $readmemb like this:

module RAM_IN (pix_val, indx);


input [0:5] indx;
output [31:0] pix_val;


reg [31:0] pix_val;
reg [31:0] in_ram [0:4];

always @ (indx)
pix_val = in_ram [indx];

initial
begin
$readmemb("in_ram.txt", in_ram);
end

The purpose of reading this file, is to initially load 100 binary values (wich simulate the pixel intensity of a 10x10 image) one by one into the top module (which is going to process and spit a result later...)

I created a .txt file which looks content exactly like this

11111111000000000000000000000000
10010111000000000000000000000000
00110110000000000000000000000000
00111110000000000000000000000000
00111111000000000000000000000000 

When I simulate, modelsim show me memory filled with xxxxxxxxxxxxxxxxx (dont care), it looks like isn't loading anything to the memory.

I don't know what I'm doing wrong. Likely isnt the dispossition of the numbers in the .txt file. Maybe is because I'm intending to load file with $readmemb in another module which is not testbench?

PD: The simulation of this process of filling the memory I'm doing only for practical purpose, the final intention is to put the Top module design into a full SoC which I think I will do using QSYS. But I'm very new at this so I'm still studying. Any help will be much appreciated!!!


Solution

  • I already fixed this. The problem is that modelsim couldn't find the .txt file, I don't know where could be the predetermined location for such of files, but looking in internet, I found that I can declare in the Ram module, the exact path like this

    initial
    begin
    $readmemb("C:/altera/15.0/Prueba5/in_ram.txt", in_ram);
    end
    

    Now modelsim is loading the correct data. Thanks everybody.