verilog code to find a single max value for an input that has 1000 samples values

Question

i want to find a single max value for an input signal that has 1000 decimal values that is read from a memory once every Positive clk edge. i did the following rough code for finding max value but it didn't give me the correct max value/number please help me so i can find a single max value in these 1000 values of input signal.

module(input clk, input [15:0]din, output [15:0]dout);
reg [15:0] max=0;

always @ (posedge clk)
if(din>max)
max<=din;
else
max<=0;

assign dout=max;
endmodule

Answer 1

Assumption 1:

If your memory read operation of 1000 valuation is out of your finding max value module then no need to track how many values are read.

module find_max (input         clk, 
                 input  [15:0] din, 
                 output [15:0] dout
               );

reg [15:0] max=0;

always @ (posedge clk)
begin
  if(din > max)
    max <= din;
  else
    max <= max;
end

assign dout = max;

endmodule

Your max value reflected in output after next cycle of being fed to find_max module.

Assumption 2:

If your outof find_max module not taking care of total number of valuation read then we just required one counter which track the number of cycles or valuation arrived.

module find_max (input         clk, 
                 input  [15:0] din, 
                 output [15:0] dout
               );

reg [15:0] max=0;
reg [ 9:0] cnt=0;

always @ (posedge clk)
begin
  cnt <= cnt + 1'b1;
  if(din > max)
    max <= din;
  else
    max <= max;
end

assign dout = (cnt == 10'd1000) ? max : 16'd0;

endmodule

We need not to store value of 1000 sample because we have to find only max value.