Verilog code for wighted average circuit

I am trying to synthesize a weighted sum circuit which will essentially implement the following equation,

out=out+a[i]*w[i] , where i=0,1..n

I have written the following code but synthesizing in design vision environment generates error as following

ELAB-368 (error) %s Net '%s', or a directly connected net, is driven by more than one source, and at least one source is a constant net.

module weighted_sum #(parameter n=10)(input [7:0] a[3:0], input [7:0] w[3:0], output [7:0] out);

assign out=0;
genvar i;
generate
for (i=0;i<n;i=i+1) begin:block1
out=out+a[i]*b[i];
end
endgenerate
endmodule

Any direction is appreciated.

Thanks Farhana

Solution

You cannot use a generate loop for this. generate is for replicating hardware. You want to logic, which should use an always block:

always_comb begin // SystemVerilog use "always_comb", Verilog use "always @*"
  out = 0;
  for (int i=0;i<n;i=i+1) begin
    out += a[i]*b[i];
  end
end

FYI, Verilog does not support multi-dimensional arrays on the port-list (ex input [7:0] a[3:0]). Verilog only supports vector type ports (aka single dimension packed arrays). SystemVerilog does support multi-dimensional arrays on ports, but some tools may have limitations on support so refer to your manuals and experiment.

Also, your module header does not scale. a & b will always be 4 entries of 8bits, and out will likely overflow. I suggest the following module header:

module weighted_sum #(parameter N=10)(
  input [7:0] a[N], input [7:0] w[N], // scaling input depth
  output logic [14+N:0] out); // scaling for overflow protection