Variables in testbench mostly are instantiated as bit rather than reg. But bit is just 2 state variable (0 and 1), reg is 4 state variable (0,1,x and z). Why people used bit as testbench variables? I took over an old project and all the testbench variables were bit. So when the checker perform checks like
if (data_rtl === data_expected) // reg[63:0] data_rtl, bit[63:0] data_expected
I couldn't perform X check on the data_expected side. Certainly it's common to use bit, why people are doing this? What's the advantage of bit over reg in systemverilog ?
Generally, there no need for 4-state types in the stimulus generation and prediction components of your testbench. Two-state simulation has the benefit of less memory overhead, which effectively doubles the size of your data caches. You basically just need to check for X's at the proper time in the interface between the testbench and DUT. The generation and propagation of X's in a design is a broad topic in itself. Most simulations are grossly inaccurate in either being too optimistic or too pessimistic when it comes to X's in different areas of your design. Sometimes, it's better to use static analysis (timing or formal) tools in these situation.