Confused between latch and flip-flop
If a latch based and gate clock gating technique is used then what would be the behaviour of latch for this below schematic. Can anybody tell the expected behaviour for the same?
As latch doesn't have clock but schematic shows here and method it self say, to give inverted clock to latch. Now If latch has clock then it is no more latch! It becomes flip-flop.
Try to elaborate word latch and actual latch in digital-logic.
Clock gating is simply control mechanism over clocking of sequential elements in the design, as your question is directly for code! It seems worthless to give it directly, instead here you can see the concept of clock gating, which is more probably useful for power-saving.
See below image,
As flow of clock stopped on control signal, clock frequency becomes 0 Hz and that will lead us to power saving.
Static power consumption:
P_static = I_static x Vdd
Dynamic power consumption:
P_dynamic = C_load x (Vdd)^2 x frequency of clock
If frequency is not there then P_dynamic should be zero ideally.
For RTL of that please refer above schematic and design accordingly. But here behaviour of latch is like flop, because it just latch EN on negedge of CLK, expected behaviour of this latch is flop.
For Digital-System both latch and flip-flop has different meaning.