Converting VHDL to Verilog

I am trying to convert the vhdl code below to verilog, and it is not working properly. I have already done most of it, but I think I may have converted the VHDL keyword others incorrectly. Could anyone please help?

VHDL Code

entity debounce is
Port ( clk : in  STD_LOGIC;
       i : in  STD_LOGIC;
       o : out  STD_LOGIC);
end debounce;

architecture Behavioral of debounce is
    signal c : unsigned(23 downto 0);
begin
   process(clk)
   begin
      if rising_edge(clk) then
         if i = '1' then
            if c = x"FFFFFF" then
               o <= '1';
            else
               o <= '0';
            end if;
            c <= c+1;
         else
            c <= (others => '0');   --LINE IN QUESTION
            o <= '0';
         end if;
      end if;
  end process;
end Behavioral;

Verilog Code Updated with Toolic's Suggestions

module debounce(input clk, input i, output o); 
    reg unsigned [23:0] c;
    reg out_temp;

    always @(posedge clk)begin
        if(i == 1)begin
            if(c==24'hFFFFFF)begin
                out_temp <= 1'b1;           
            end
            else begin
                out_temp <= 1'b0;
            end
            c <= c+1'b1;
        end
        else begin
            c <= {24{1'b0}};
            out_temp <= 1'b0; 
        end
    end
    assign o = out_temp;
 endmodule

Solution

When you say "see if it works", are you simulating? If not, it's a good idea to do so. Here is a simple testbench that compares the two versions:

module debounceTest; 
    reg clk=1'b0;
    reg i=1'b1;
    reg error=1'b0;
    wire oVerilog, oVHDL;
    integer k;

    debounceVerilog UUTverilog (clk, i, oVerilog);

    debounceVHD UUTvhdl (clk, i, oVHDL);

    always
      #5 clk = ~clk;

    initial begin
    for (k=0; k<2**26; k=k+1) begin
      if ((k%(2**25))==0)
        i = ~i;
      #10;
      end
    $stop;
    end

    always @* begin
      #1;
      if (oVHDL!==oVerilog)
        error = 1'b1;
    end

 endmodule

(Actually, I reduced the size of the counters in the models and simulated for a shorter time - this took rather a long time to simulate).

Why not do this for all these blocks that you are translating from one language to the other?