VHDL FILE_OPEN does not return correct status

Question

I have a procedure in VHDL that reads a line from file and is supposed to assign signal values based on individual characters of the line. The problem i am facing is that my FILE_OPEN statement seems not be working.

FILE_OPEN(fstatus, mem_file, "H:\memfile.dat", READ_MODE);

The fstatus always have OPEN_OK if uninitialized or the value it is initialized to never changes. The complete code of the procedure is given below.

library IEEE; 
use IEEE.STD_LOGIC_1164.all; use STD.TEXTIO.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
--use ieee.std_logic_1164_additions.all
entity imem is -- instruction memory
 port(a:  in  STD_LOGIC_VECTOR(5 downto 0);
      rd: out STD_LOGIC_VECTOR(31 downto 0));
 end;
architecture behave of imem is
begin
 process is
   file mem_file: TEXT;
   variable L, my_line: line;
   variable L_ch : string(1 to 8);
   variable ch, charac: character;
   variable i, index, result: integer;
   variable valid : boolean; -- to record whether a read is successful or not
   variable fstatus: FILE_OPEN_STATUS;
   type ramtype is array (63 downto 0) of STD_LOGIC_VECTOR(31 downto 0);
   variable mem: ramtype;
begin
  -- initialize memory from file
for i in 0 to 63 loop -- set all contents low
  mem(i) := (others => '0'); 
end loop;
index := 0; 
 --fstatus := NAME_ERROR;
FILE_OPEN(fstatus, mem_file, "H:\memfile.dat", READ_MODE);
 report "Got status from file: '" & FILE_OPEN_STATUS'image(fstatus) & "'";

 IF fstatus = OPEN_OK THEN

while not endfile(mem_file) loop


  readline(mem_file, L);
    report "Got line from file: '" & L.all & "'";
    result := 0;    
  for i in 1 to 8 loop
    read(L, ch, valid);
      --write(my_line, string'(L_ch));    -- formatting
      --writeline(output, my_line);

      if (L'length = 0) then report "line empty " & integer'image(index)
            severity error;
      end if;


      --ch := L_ch(i);
      read(L, charac);

    if '0' <= ch and ch <= '9' then 
        result := character'pos(ch) - character'pos('0');
    elsif 'a' <= ch and ch <= 'f' then
       result := character'pos(ch) - character'pos('a')+10;
    else report "Format error on line " & integer'image(index) & character'image(ch) & character'image(charac) & boolean'image(valid) --& to_string(L_ch)
         severity error;
    end if;
    mem(index)(35-i*4 downto 32-i*4) :=std_logic_vector(to_unsigned(result,4));
  end loop;
  index := index + 1;
end loop;



-- read memory
loop
  rd <= mem(to_integer(unsigned(a)));
  wait on a;
end loop;
 file_close(mem_file);
 end if;
 wait;
 end process;
end;

I am using Quartus Prime Lite for Synthesis.

Answer 1

Altera's Quartus does not support VHDLs file I/O features in synthesis. As far as I can tell, Quartus does support Verilog file I/O features in synthesis.

See the altsyncram (search for $readmemh(...)) implementation for more details on Verilog file I/O used to read *.mif files while synthesis to initialize RAMs.