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How do you make a transparent latch in Chisel?

Here is my best guess, but it doesn't look like the generated behavioral Verilog will result in a simple transparent latch when synthesized:

// DXP Latch
val dxp = config(2) & config(0)
val latch = Reg( lut.io.out )
val out = Mux( dxp, latch, lut.io.out )

I appreciate your ideas on this.

Solution

  • Chisel does not support latches. Reg() will only generate edge-triggered state elements.

    If you really want latches, you would have to modify the backend of Chisel to understand a new Latch() construct and generate the appropriate Verilog. However, this will take you down a long rabbit hole of difficulties, the first of which is you would probably be throwing away the synchronous, edge-triggered timing model (that allows things like the C++ emulator to work).

    In our experiences, any critical applications that needed some of the properties of latches will get automatically handled by the synthesis tools (like time-borrowing).