I want to read 8 bit register bit by bit. i.e first reading 0:3 , then 1:4 , then 2:5 . Reading 4 bits at one time. Below code give error when accessing register bits using integer.
module First_Module(
clock,
reset,
enable,
counter_out
);
// input ports
input clock;
input reset;
input enable;
output [3:0] counter_out;
wire clock;
wire reset;
wire enable=1'b1;
reg[3:0] counter_out=0001;
reg[9:0] line=1101101101;
reg[3:0] testPattern=1101;
reg[3:0] temp=0000;
integer IndexStart,IndexEnd;
initial
begin
IndexStart=0;
IndexEnd=3;
end
initial
#20 $finish; //finish after 20 time units
always
begin:COUNTER
\#1
$monitor ("counter Out = %d Reset = %d",counter_out,reset);
$monitor ("Temp = %d ",temp);
if(reset==1'b1)
begin
counter_out <= 4'b0000;
end// if-end
else if (enable==1'b1)
begin
counter_out= counter_out+1;
IndexEnd=IndexEnd+1;
temp=line[IndexEnd:IndexStart]; // Error at this line
end
end// always end
endmodule
Help is required .
temp=line[IndexEnd:IndexStart];
Verilog sees this a s a dynamic length selector. Which does not make sense in hardware. from Verilog 2001 a new standard for making variable location, fixed width selections (part selects) was introduced.
You should be able to use the following for 4 bit selects:
temp=line[IndexStart +: 4];
For more info see page 23 of Using the New Verilog-2001 Standard by Stuart Sutherland