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for-loopveriloghdl

Verilog - Why I can't declare multiple vars in a for statement?

I have a code like this:

generate
genvar i, j, k;
for (i = 0, j = 8, k = 0; i < 4; i = i + 1, j = j + 8, k = k + 8)
    Register Register_inst (.d(w_data), .en(decoder_out[i]), .clk(clk), .q(trunc_32_to_n_bits(reg_out, j-1, k)));
endgenerate

Is it possible to have multiple vars in a for like in other languages?

Solution

  • There are two types of for-loops in Verilog, procedural for-loops (inside a initial or always block)and generate for-loops (outside of the initial and always block). Both are restricted to simple single variable assignments.

    Typically you do not need multiple variables managed by a for-loop. In the majority of cases other values can be derived from one index. You code does not need three variables as everything can be determined from i:

    generate
genvar i;
for (i = 0; i < 4; i = i + 1)
  Register Register_inst (.d(w_data), .en(decoder_out[i]), .clk(clk), .q(reg_out[i*8 +: 8));
endgenerate

    For more on the +: array slicing operatior, refer to earlier answered questions:
    Indexing vectors and arrays with +: and What is `+:` and `-:`?

    Note: SystemVerilog supports multiple variable assignments with procedural for-loops. There is still single variable assignment restriction with generate for-loops as per IEEE Std 1800-2012.