Search code examples
fpgaintel-fpganiosquartusqsys

Multiple Interrupt Senders in one peripheral in Qsys

Using Qsys (Quartus II x64 15.0.1 build 150) I made a system with Nios2/e and several standard peripheral components. I also add my custom component with 1 MM-Slave and 2 Interrupt Senders. For each of them I set this slave as "Associated addressable interface" in Component editor during creation of _hw.tcl file.

Qsys reports no errors or warnings, but then I tried to make BSP project in Eclipse using New | Nios 2 BSP project wizard. I select "SOPC Information File name", but "CPU" ComboBox remains empty and error appears: "No Nios II CPU Found".

Then I launch BSP Editor from main menu: Nios 2 | BSP Editor and press File | New Nios 2 BSP. I again provide SOPC file and this tool found CPU, but also reports the error: "Can only have at most one IRQ associated with the following slaves of module "my_component" : mm_slave."

I then returned to Qsys and remove one of Interrupt Senders and this time everything works fine, but I need to generate more than one interrupt.

So what to do if you have Nios2/e connected to custom peripheral with 1 MM-Slave and several Interrupt Senders?

I have some ideas but don't like them:

  1. Add MM-Slave for each irq (it looks like waste of resources).

  2. Do not specify "Associated addressable interface" in Component editor (it is by the way works, but I don't know will it work properly all the time). What this option really do? I was imprecise saying that it will work, sorry for that. In reality qsys and BSP can be generated but inside BSP's system.h IRQ number will be defined as -1, so it will not work.

  3. Merge all interrupts into one wire (they all will share the same priority).

  4. Configure Interrupt Sender to have irq signal with width more than 1 (Component Editors allows to do this but reports warning: "interrupt_sender: Signal irq_many[4] of type irq must have width [1]".) As with case 2 I don't know what will happen inside Altera's generators/compilers. After Component Editor stage is finished Qsys doesn't accept such a system.

Please help.

Solution

  • At last, I have found the following:

    A. If you need many IRQ Senders inside one custom Qsys module you need one MM-Slave per each. From GUI organization it seems that you are assigning MM-Slave to the IRQ, but (as far as I understand it) it works directly opposite: IRQ is tied to MM-Slave and it may has maximum one IRQ. I didn't try to actually run it, but BSP files looks correct and everything compiles at least. I hope, that there is (or will be) a better way to achieve this.

    B. If you can share the same priority between all interrupts, than you can avoid the problem by using only 1 Interrupt Sender and thus only 1 MM-Slave. It works on dev board.