Saving Returned Value from Verilog Module

I don't understand how to save the result from a verilog module.

I declare something like this: andgate myand(x,y,andout);

module andgate(a,b, out);
    input a,b;
    output out;
    wire out;
    assign out = a & b;
endmodule

But this returns a pointer that seems to evaluate whenever you use the pointer.

So: assign n = andgate just makes n into a copy of the andgate pointer. I want to save the result from the module so I can reuse that value.

Thanks

Solution

You have tagged the question with assembly and verilog, and the discussion of pointers indicates a misunderstanding of Verilog.

While most programming languages call functions and tasks, which verilog can do, Verilogs main purpose is hardware description.

A module is not a function that is called, it is a representation of a physical unit of hardware.

For example:

andgate myand1(x,y,andout);

Above implies a single and gate.

andgate myand1(x,y,andout);
andgate myand2(x,y,andout2);

The example above does not use two clock cycles or make two calls to the same hardware. It does imply two units of hardware.

The outputs andout and andout2 are combinatorial wires.

Assuming that n is declared a wire:

assign n = andgate;

this just joins n to the andgate wire, they will always have the same value. There is no copy, they are literally the same wire holding the exact same value.

You might want to use flip-flops to hold and change values, a flip-flop only changes it value on a clock edge.

A basic flip-flop will look like:

reg n; 
always @(posedge clk) begin
  n <= andgate;
end