I was wondering if it is possible to encode an instruction like:
add rax,[address]
where <address> is a full 64-bit address pointing to a 64-bit value. NASM seems to simply truncate the address and encode it as a 32-bit address. The only form of 64-bit addressing (with a direct address) that seems to work is:
mov rax,[qword address]
which is encoded by NASM using REX.W=1 and special opcodes of MOV with direct addressing. Using REX.W with the add instruction merely makes it interpret the target address as containing a 64-bit value, but doesn't allow for the specification of a 64-bit address. But I am curious if there is another way.
(By the way, due to this problem I am for now using the RIP-relative addressing).
Can anyone confirm that the direct 64-bit addressing form is impossible?
The amd64 architecture has no addressing mode with a 64 bit displacement except in some special cases. Instead, use rip relative addressing which should be fine if your binary is less than 2 GB in size.