Verilog :errors.Invalid use of input signal <ck> as target

Question

I can't figure out , where this errors.Invalid use of input signal <ck> as target error is coming from?

module register
  #(parameter  Width = 8)
   (output reg [Width-1:0] out,
    input      [Width-1:0] in,
    input                  clear, load, clock);

 always @(posedge clock)
   if (~clear)
     out<= 0;
  else if (~load)
    out<=in;
endmodule

module adder
  #(parameter Width = 8)
  (input  [Width-1:0]  a,b,
   output [Width-1:0] sum);
   assign sum = a + b;
endmodule


module compareLT // compares a < b
  #(parameter Width = 8)
  (input  [Width-1:0] a, b,
   output             out);
   assign  out = a < b;
endmodule

module compareLEQ // compares a <= b
  #(parameter Width = 8)
  (input [Width-1:0] a, b,
   output            out);
   assign out = a <= b;
endmodule


module roshanpoop
  #(parameter Width = 8)
   (input                ck, reset,
    input   [Width-1:0]  yln,
    output  [Width-1:0]  y, x);

    wire [Width-1:0] i, addiOut, addxOut;
    wire  yLoad, yClear, xLoad, xClear, iLoad,iClear;

    register  #(Width) I (i, addiOut, iClear, iLoad, ck);
    register  #(Width) Y (y, yIn, yClear, yLoad, ck);
    register  #(Width) X (x, addxOut, xClear, xLoad, ck);

    adder  #(Width)  addI (addiOut, 'b1, i),
    addX (x, y, addxOut);
    compareLT   #(Width)  cmpX (x, 'b0, xLT0);
    compareLEQ  #(Width)  cmpI (i, 'd10, iLEQ10);
    fsm ctl     (xLT0,iLEQ10  ,yLoad, yClear, xLoad, xClear, iLoad,iClear, ck, reset);
endmodule


module fsm
 (input LT,LEQ, ck, reset,
  output reg  yLoad, yClear, xLoad, xClear, iLoad, iClear);
  reg [2:0]  cState, nState;

  always @(posedge ck,negedge reset)
    if (~reset)
      cState <= 0;
    else
      cState <= nState;

  always@(cState, LT,LEQ)
    case (cState)
      3'b00:  begin  //stateA
        yLoad = 1; yClear = 1; xLoad = 1; xClear = 0;
        iLoad = 1; iClear = 0; nState = 3'b001;
      end
      3'b001: begin  // state B
        yLoad = 1; yClear = 1; xLoad = 0; xClear = 1;
        iLoad = 0; iClear = 1; nState = 3'b010;
      end
      3'b010: begin  //state C
        yLoad = 1; yClear = 1; xLoad = 1; xClear = 1;
        iLoad = 1; iClear = 1;
        if(LEQ)         nState = 3'b001;
        if(~LEQ & LT)   nState = 3'b011;
        if (~LEQ & ~LT) nState = 3'b100;
      end
      3'b011:  begin  //state D
        yLoad = 1; yClear = 0; xLoad = 1; xClear = 1;
        iLoad = 1; iClear = 1; nState = 3'b101;
      end
      3'b100: begin  //state E
        yLoad = 1; yClear = 1; xLoad = 1; xClear = 0;
        iLoad = 1; iClear = 1; nState = 3'b101;
      end
      default: begin // required to satisfy combinational synthesis rules
        yLoad = 1; yClear = 1; xLoad = 1; xClear = 1;
        iLoad = 1; iClear = 1;nState = 3'b000;
        $display("Oops, unknown state: %b", cState);
      end
    endcase
endmodule

error:

 line no:70
 Invalid use of input signal ck as target,
 Invalid use of input signal target as target.

In module roshanpoop above mentioned error are coming . what might be the problem ?

Answer 1

The error is caused by this instantiation:

fsm ctl     (xLT0,iLEQ10  ,yLoad, yClear, xLoad, xClear, iLoad,iClear, ck, reset);

of the module:

module fsm
 (input LT,LEQ, ck, reset,
  output reg  yLoad, yClear, xLoad, xClear, iLoad, iClear);

You are using positional instantiation, which is not recomended, because it makes the task of maintaining your module more difficult (think, for example, if you want to add signals to your module: if you add it in the middle of the module's definition, all remaining signals will be wrongly connected).

Here, the use of positional instantiation has caused signal ck from the top module to be connected to iLoad, which is an output signal from fsm, so you are trying to put a value to a input only signal ck.

The way to have it right is to use explicit instantiation, where each signal from the module is explicitly named and assigned to a signal from the top module, like this:

fsm ctl     (.LT(xLT0),
             .LEQ(iLEQ10),
             .yLoad(yLoad),
             .yClear(yClear),
             .xLoad(xLoad),
             .xClear(xClear),
             .iLoad(iLoad),
             .iClear(iClear),
             .ck(ck),
             .reset(reset)
         );

So, regardless of where in the argument list you put signal clk it will be always connected to the right signal inside the module.