Others => '1' statement in Verilog

Question

I have used VHDL all my life and only been using Verilog for a short time, I have to create a logic in Verilog for a very large array and assign it to 1 or 0 depending on the condition of an input.

Here is my VHDL code

 if (data_track == '1' ) then
            my_array(MAX-1:MIN) <= (others=> '1');
 else
            my_array(MAX-1:MIN) <= (others=> '0');
 end if;

MAX and MIN are parameters for the block, set during the synthesis depending on the type of system we are accessing.

Is there a way to do this in Verilog easily?

Answer 1

A mix of parameter with curly braces will help in resolving (the inner curly brace will act as replication operator)

Code eg:

    parameter MAX = 16;

    assign high_val = 1'b1;
    assign low_val = 1'b0;

    if ( data_track ==1'b1) 
    my_array[MAX-1:MIN] <= {MAX{high_val}};
    else
    my_array[MAX-1:MIN] <= {MAX{low_val}};

Here in the above code the if statement with curly brace will propogate MSB to LSB with 1 values resulting in all 1's in our case 16 then result will be a 16'b1111111111111111 and it is the vice versa for else condition