I am trying to implement a QAM modulator in SystemVerilog on a Virtex 7 with Xilinx Vivado and I am stuck with the generation of the sin and cos of the local oscillator.
More specifically, I have as inputs the I and Q signals (3 bits each) and I have to multiply them with a cosine and a sine wave, respectively. The multiplication works fine but I need an IP to generate the cosine and the sine at a give frequency.
In that purpose, I have deeply read the documentation of the DDS Compiler v6.0 provided at the following link but I am still stuck: http://www.xilinx.com/support/documentation/ip_documentation/dds_compiler/v6_0/pg141-dds-compiler.pdf
Does anyone have any suggestion or example code to help me ?
I thank you in advance
Please, find hereunder some screenshots and my example code. What I don't understand is why the sin/cos take theses "strange" values. Did I use the dds_compiler correctly ?
screenshots and Vivado project (I don't have yet the authority to post it directly): https://www.dropbox.com/s/xi5hralr2klk37s/dds_compiler.zip?dl=0
modulator.sv :
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 31.03.2015 07:41:17
// Design Name:
// Module Name: modulator
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module modulator(
input logic clk,
input logic [2:0] I,
input logic [2:0] Q,
output logic [18:0] p1,
output logic [18:0] p2,
output logic tvalid
);
// internal signals
logic [15:0] sin,cos;
// carrier generation
dds_compiler_0 dds_compiler_0_inst(
.aclk(clk),
.m_axis_data_tdata({sin,cos}),
.m_axis_data_tvalid(tvalid)
);
// multiplier
mult_gen_0 mult_gen_0_inst_1(
.CLK(clk),
.A(I),
.B(cos),
.P(p1)
);
mult_gen_0 mult_gen_0_inst_2(
.CLK(clk),
.A(Q),
.B(sin),
.P(p2)
);
endmodule
modulator_testbench.sv :
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 31.03.2015 07:41:17
// Design Name:
// Module Name: modulator_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module modulator_testbench();
// test signals
logic clk;
logic [2:0] I, Q;
logic [18:0] p1,p2;
logic tvalid;
// generate clock
always begin clk=1; #5; clk=0; #5; end
// instantiate dut
modulator dut(
.clk(clk),
.I(I),
.Q(Q),
.p1(p1),
.p2(p2),
.tvalid(tvalid)
);
// start simulation
initial begin
#65;
I=3'd1; Q=3'd1; #10;
I=-3'd1; Q=3'd1; #10;
I=3'd3; Q=-3'd3; #10;
I=-3'd3; Q=-3'd1; #10;
I=3'd1; Q=-3'd1; #10;
end
endmodule
For posteriority, the full code is available here; details and explanations can be found in the paper.
Everything worked fine thanks to the comment of dieli. I summary it here in case it could help someone else:
The set phase increment ("1100" in my case) is added every clock cycle. Therefore, since I use a 16-bit bus, I need about 5461 clock cycles for one sin/cos. We can then easily compute the output frequency using the formula given in the datasheet. To see the sin/cos wave with Vivado, right-click on the sin/cos signal and select 'waveform style' and then 'Analog'. (Be sure that you run the simulation for enough time.)