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vhdlmodelsimintel-fpgaquartus

Is setting signal values to unitialized acceptable?

To achieve something in my VHDL code I'm currently doing:

tmpOutput <= "UUUUUUUU";

Is that seen as something wrong entirely? Also, can this bring problems when synthesizing the design?

Thanks a lot!

Solution

  • 'U' is not undefined, but uninitialized. It is perfectly legal, but weird since a signal would logically not go from uninitialized to a value back to uninitialized.

    It may be better to use 'X', which is unknown or '-' which is don't care. As for what a synthesis tool will do with it, it will either consider it as don't care or the same as '0'.