I am implementing TxRx on Zynq chip. My design is working, but I would like to make optimization of it. Based on report my DSP slices are not utilized. I would like to make multiplication operations on DSP slices. I am just starting with FPGAs. Are there any guidelines hot to target FPGA DSP slices for multiplication operation from my Verilog code. How should I write functions where I write multiplication?
Kind Regards,
Yes they are, basically you should use pipeline registers and make sure you don't use any illegal usage of the DSP blocks. One example is the DSPs registers in Xilinx's FPGA don't have an asynchronous reset.
The best way to learn how to use DSPs in Verilog with Xilinx's FPGAs is to read the synthesis guide. You will find both guidelines and examples in VHDL and Verilog that will map to DSPs, including use of the pre-adder and accumulator should you require them.
You will also find that Vivado has a section in its synthesis report that shows every dsp used and how they are configured (mode and width). Whenever you feel your code should map to a DSP, it's easy to verify that Xilinx actually did what you intended.