Verilog Latch in always@(posedge clk)

Question

If I understand latch correctly, it is created in combinational block in which not all possible conditions are declared when assigning a variable to a value. How am I getting a latch in my sequential block?

When I compiled my code via Quartus, it retured 2 Fmax, which indicates I have a latch.

   always@(posedge clk or negedge nreset) begin
      case(counter)
         0: begin
            if(state == IDLE) begin
               // DOES SOMETHING
            end
         end

         1: begin
           // DOES ASSIGNMENT
         end // PROLOG

         81: begin
           // DOES ASSIGNMENT
         end // EPILOG


         82: begin
            // DOES ASSIGNMENT
         end // POSTPROC

         default: begin
            // DOES ASSIGNMENT
         end // ROUNDS

      endcase  

I have checked each of the cases, and made sure all assignments are non-blocking. Any idea why I might be latching?

My code is computing SHA1

I have 2 always@(posedge clk), one computes the next Wt, and the above computes the next A,B,C,D,E value.

Answer 1

There is no else on your if statement.The synthesizer is confused as to what needs to happen next, thus inferring latches.

If that is not intended but instead simply what you wrote for the stack overflow example then the problem may be in your other always block.

A latch is simply a Flip Flop without a clock. The reason synthesizers think they are bad is because they can potentially cause timing errors. Latches are not always a problem either, in fact sometimes as you probably already know, they are intentional.

Check your assign statements, and see if you have any regs declared outside of an always block which is initialized to 0 or some value.

In that case you might like to try the initial block. Syntax:

 initial
 begin

 value = 0;
 input = 0; // or something

 end