Check if a signal is active for 100 clock ticks?

Question

I have one input and one output. I want to set the output to 1 if the input was active for 100 ticks (clock cycles).

module check_100(
   input wire clock,
   input wire reset,
   input wire in_a,
   output reg out_a);  

reg[10:0] counter;  

always @(posedge clock) begin
    counter <= counter + 1;
    if(in_a && (counter == 100)) begin
        out_a <= 1;
    end
end

But, it doesn't seem to work properly. Is this a good way to check whether a signal is 100 ticks/cycles active or not?

Answer 1

One way is to use a continuous assignment to set your output when count==100. When the input goes low, the counter is reset. Hold the count value when it hits 100.

module check_100(
   input wire clock,
   input wire reset,
   input wire in_a,
   output wire out_a
);  

reg [10:0] counter;  

assign out_a = counter == 100;

always @(posedge clock) begin
    if (reset) begin
        counter <= 0;
    end else if (!in_a) begin
        counter <= 0;
    end else if (counter < 100) begin
        counter <= counter + 1;
    end
end

endmodule