I wrote the following testbench in verilog that writes a file and then reads the values back.
// Verilog Test Fixture Template
`timescale 1 ns / 1 ps
module Read_And_Write_File;
/*Add signals used for verification of the values written in SRAM*/
integer handle, channels,index;
reg [15:0] memory [22:0];
reg [22:0] mem_idx;
reg [15:0] val;
initial begin
/*Write the memory file 'SRAM.dat'using the values that are supposed to be in the SRAM after the simulation*/
handle = $fopen("SRAM.dat");
channels = handle | 1;
$display("Generating contents of file SRAM.dat");
$fdisplay(channels, "@1");
val = 16'h2121;
for(index = 0; index < 60; index = index + 1)
begin
$fdisplay(channels, "%h", val);
val=val+16'h1;
end
$fclose(handle);
/*Read the values in the file 'SRAM.dat' and compare the values with the values that were actually written in the SRAM*/
$readmemh("SRAM.dat", memory);
$display("\nContents of memory array");
mem_idx=23'h1;
for(index = 0; index < 60; index = index + 1)
begin
$display("The Value is:%h and index in hex %h",memory[mem_idx],mem_idx);
mem_idx=mem_idx+23'h1;
end
end
endmodule
Writting the file seems to be ok. However when reading with 'readmemh' I get an error as follows:
ERROR: Too many words specified in datafile SRAM.dat
And I also do not get the correct values after reading the 23 values:
The Value is:2135 and index in hex 000015
The Value is:2136 and index in hex 000016
The Value is:xxxx and index in hex 000017
The Value is:xxxx and index in hex 000018
Any help on how to read back the correct values and fix the error is appreciated. The simulation was done in Isim.
Nevermind, I found my mistake. reg [15:0] memory [22:0] should be reg [15:0] memory [60:0], since it refers to total number words in the memory. I though it was interpreted as the bits needed to represent the address.