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if-statementvhdl

VHDL If/Else statement

I am trying to work on a lab for a school project. we are supposed to be eventually making a program that displays signed integer values to an altera board. This is one of the steps along the way and i am stuck. I cant figure out why this if/else statement wont compile, I am new to VHDL, please help.

-----------------------------------------------------------------
-- circuit for converting a 4-bit signed integer
-- to a 1-bit sign and a 4-bit absolute value
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity sgnabs4 is
   port (X    : in std_logic_vector(3 downto 0);
       sgn  : out std_logic;
       Xabs : out std_logic_vector(3 downto 0));
end sgnabs4;

architecture sgnabs4_arch of sgnabs4 is

    component twos_complement4 is
        port (A : in std_logic_vector(3 downto 0);
            T : out std_logic_vector(3 downto 0));
    end component twos_complement4;

      -- you may define internal signals here as you feel necessary
        signal That: std_logic_vector(3 downto 0);
        signal Ahat: std_logic_vector(3 downto 0);

begin


    twos_complement4_0: twos_complement4
        port map(T => That, A=> Ahat);

  sgn <= That(3);


  if (sgn = '1') then
    sgn => Xabs(3);
    Xabs(2) <= not X(2);
    Xabs(1) <= not X(1); 
    Xabs(0) <= not X(0);


  else

    Xabs(3) <= '0';
    Xabs(2) <= X(2);
    Xabs(1) <= X(1); 
    Xabs(0) <= X(0);

  end if;

end sgnabs4_arch;
Solution

  • Andy's answer may be valid, but it doesn't explain what's wrong with yours at all. So:

    As sebs pointed out in the comments, your if statement needs to be in a process. if statements are sequential; only concurrent statements are allowed outside processes in architecture bodies.

    While the two fixes sebs pointed out may allow your code to compile (depends on how you handle another bit that I'll get to in a minute), it still won't work.

    • Your component instance twos_complement4_0 has Ahat mapped to its input port and That mapped to its output port, but you don't assign a value to Ahat anywhere in your code, so what will That be? Probably not anything useful. If you copied and pasted this, you need to understand what it does to be able to modify it appropriately. Look for a tutorial, specifically on component instantiation and port mapping.
    • Did you also mean to leave the line sgn <= That(3);? You can't drive sgn from multiple places. The process is one, the concurrent statement appears to be intended to be another (though maybe not - hard to tell). This won't work.

    It looks like what you're trying to do is:

    • get the two's complement of your input.
    • If the input is negative, use the two's complement, else use the original number (and output the appropriate value on sgn).

    The closest thing to your original code that does that would be:

    architecture sgnabs4_arch of sgnabs4 is

  component twos_complement4 is
      port (A : in std_logic_vector(3 downto 0);
            T : out std_logic_vector(3 downto 0));
  end component twos_complement4;

  signal tmp : std_logic_vector(3 downto 0);

begin

  twos_complement4_0 : twos_complement4
    port map (A => X, T => tmp);

  sgn <= X(3);

  process (X, tmp)
  begin
    if (X(3) = '1') then
      Xabs <= tmp;
    else
      Xabs <= X;
    end if;
  end process;

end sgnabs4_arch;

    tmp is the inverse of X. If X is negative (i.e. its sign bit is '1'), output the inverse, otherwise output X. This may not be the most efficient way to accomplish this task, as Andy alludes to, but it should work, and may be what you intended.