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verilogsystem-verilog

Preventing argument substitution in Systemverilog text replacement macro

`define CONNECT(i) \
  some_mod inst1 (.i(i));

module test ();
 logic a;
 `CONNECT(a)
endmodule

In the CONNECT macro, how do I prevent a being swapped in for i in the ".i" portion of some_mod inst1 (.i(i));? I am looking for an expanded version like this:

module test ();
 logic a;
 some_mod inst1 (.i(a));
endmodule

instead of below version which is wrong

module test ();
 logic a;
 some_mod inst1 (.a(a));
endmodule

I understand I can either make some_mod's port name to be something other than i or change macro argument name from i to something else. I am just wondering if what I want to do is feasible at all.

Solution

  • Since you already know all the port names of your some_mod module, you just need to choose a unique string for your macro. Assuming some_mod does not have a port named SIG:

    `define CONNECT(SIG) \
  some_mod inst1 (.i(SIG));

    UPDATE: To answer the new question: No, after referring to the IEEE Std 1800-2012, it is not feasible to selectively avoid some substitutions.

    UPDATE 2: As Stan has demonstrated, there is a tricky solution; since it is not straightforward, it should be heavily commented.