System Verilog Model inside VHDL TestBench, Real port issue

Question

I have a SV subblock with real inputs :

`include "Components.sv"

    module EPO_REG #(parameter bit ExtIso = 1, real th_high = 5.5 , real th_low = 4.2)(input bit EPO_SETPOINT, NVC_PMOS_ON, NVC_NMOS_ON ,**input var real IVcc5, Viso, Vcc5_ext** ,output real EpoPower, Vcc5, IEPO);

     real Iin;
     real Vout;
     real Vcap;
     real Ids_nmos;
    ...........
    ...........

I put this block in a VHDL top level (or Testbench) for example in this way:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.MATH_REAL.ALL;

entity EPO_REG_WRAP is

    GENERIC (
      ExtIso     : bit := '1';   
      th_high    : REAL := 5.5;   
      th_low     : REAL := 4.2   
      );
    PORT (
      NVC_PMOS_ON  : IN  STD_LOGIC;
      NVC_NMOS_ON  : IN  STD_LOGIC;
      EPO_SETPOINT : IN  STD_LOGIC; 
      Vcc5_ext     : IN  REAL;
      IVcc5        : IN  REAL;
      Viso         : IN  REAL;
      Vcc5         : OUT REAL;  
      EpoPower     : OUT REAL;  
      IEPO         : OUT REAL 
      );
end;

architecture beh of EPO_REG_WRAP is

COMPONENT EPO_REG  
    GENERIC (
      ExtIso     : bit := '1';   
      th_high    : REAL := 5.5;   
      th_low     : REAL := 4.2   
      );
    PORT (
      NVC_PMOS_ON  : IN  STD_LOGIC;
      NVC_NMOS_ON  : IN  STD_LOGIC;
      EPO_SETPOINT : IN  STD_LOGIC; 
      Vcc5_ext     : IN  REAL;
      IVcc5        : IN  REAL;
      Viso         : IN  REAL;
      Vcc5         : OUT REAL;  
      EpoPower     : OUT REAL;  
      IEPO         : OUT REAL  
      );
end component;

begin

UEPO_REG: EPO_REG 
        GENERIC MAP(
          ExtIso     => '1',   
          th_high    => 5.5,  
          th_low    => 4.2 
        )
        PORT MAP(
            NVC_PMOS_ON  => NVC_PMOS_ON,
            NVC_NMOS_ON  => NVC_NMOS_ON,
            EPO_SETPOINT => EPO_SETPOINT,
            Vcc5_ext         => Vcc5_ext,
            IVcc5 => IVCC5,
            Viso => Viso,
            EpoPower => EpoPower,
            Vcc5 => Vcc5,
            IEPO => IEPO
        );

end;

But I get following errors during elaboration:

ncelab: *E,MAINVR: Mapping of Verilog var port of mode IN with VHDL port/signal of entity/component 'VCC5_EXT' (File : EPO_REG_WRAP.vhd, line: 42, position: 13) is not supported.
ncelab: *E,MAINVR: Mapping of Verilog var port of mode IN with VHDL port/signal of entity/component 'IVCC5' (File : EPO_REG_WRAP.vhd, line: 43, position: 10) is not supported.
ncelab: *E,MAINVR: Mapping of Verilog var port of mode IN with VHDL port/signal of entity/component 'VISO' (File :EPO_REG_WRAP.vhd, line: 44, position: 9) is not supported.

As far as I know SV supports real values on ports. What I'm doing wrong?

Answer 1

I solved by switching from SV-2008 to SV-2012.

SV-2008 does not allow to be driven from a real net but it manage only variables. SV-2012 allows to manage signals.