Can Verilog/Systemverilog/VHDL be considered actor oriented programming languages?

Question

These languages provide modules which are inherently concurrent and can handle asynchronous messages pretty neat (through ports). Keeping aside the fact that they cannot spawn module instances at runtime, do they qualify as actor based programming languages?

Thanks

EDIT:

What I'm really looking for is how well the language semantics can be used to "model" actors, rather than how a simulator would handle the code (of course, they are all event-driven underneath; and further down, we end up with transistors :-) ).

So if I create a bunch of Ip4Routers like this,

module Ip4Router (
    inout interface_t intrf1,    // Port that can atomically send/rcv packets
    inout interface_t intrf2, ...
);
    always @(intrf1) begin // Activity on intrf1
        if (intrf1.valid & intrf1.ipaddr != myaddr && ...) begin
            intrf2.valid <= .. // atomically bang data on intrf2 + other stuff
        end
    end
    //...
endmodule

module test;
    interface_t intrf1[1001];
    Ip4Router r1(intrf1[0], intrf1[1])
    Ip4Router r2...;          // Create and wire up 1000 routers in some topology...
endmodule

would the routers qualify to be (miniature) actors?

Answer 1

While these HDL's are not inherently designed as actor oriented languages, there has been multiple efforts to model abstract asynchronous message-passing using them. There are various examples of modeling Communicating Sequential Processes (CSP) in Verilog/SystemVerilog/VHDL/SystemC. Although they are meant to be used to design hardware and test environments, with a little bit of effort they can be used to "mimic" such higher level modeling language. The obvious reason for doing this is to take advantage of the existing powerful compilers and simulation tools for these language and not creating yet another new language.

For example, "SystemVerilogCSP" models CSP-like communication channels and abstract message passing using SystemVerilog's interfaces. While the communication channels are implemented using handshake protocols, from the user's perspective of this package, they are just atomic and blocking actions. See Figure 2 in this paper, in which two concurrent modules communicate through blocking CSP-like communication actions.

Moreover, Verilog and SystemVerilog can spawn parallel threads using fork-join constructs.