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constraintsfpgaxilinxintel-fpga

How can I achieve something similar to Xilinx' RLOC in Altera FPGAs?

I have so far not found any way to do anything similar to Xilinx' RLOC constraints for Altera FPGAs.

Does anyone know a way to do this?

For example place two FFs in the same or adjacent LABs

Solution

  • So to answer my own question, after some consultation with some Altera manuals and some trial and error, I found that this pretty much does what I want.

    module synchronizer (input wire dat_i,

                     input wire out_clk,
                     output wire dat_o);

   (* altera_attribute = "-name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2; -name SYNCHRONIZER_IDENTIFICATION \"FORCED IF ASYNCHRONOUS\"" *)
   logic [1:0]                   out_sync_reg;

   always_ff@(posedge out_clk) begin
      out_sync_reg <= {out_sync_reg[0],dat_i};
   end

   assign dat_o = out_sync_reg[1];

endmodule

    I tested this by setting global synchronizer detection to off and observed that TimeQuest found and analysed the correct paths for metastability.

    This works well even when dat_i is latched by clk_a and out_clk is driven by clk_b and where the two clocks are set as:

    set_clock_groups -asynchronous -group {clk_a}
set_clock_groups -asynchronous -group {clk_b}

    Thus creating false paths between all connections from registers clocked by clk_a to registers clocked by clk_b

    set_max/min_delay wont work since it is ignored (as stated by Altera) if the the two clocks are in different asynchronous clock groups.